Electronic components are increasingly being used as so-called wafer level packages or chip size packages. In order to meet the constant demand for ever smaller component dimensions, these components do not have housings but at most protective passivation or plastic layers, so that the dimensions thereof correspond precisely or virtually to those of the contained integrated circuit (chip). The integration of these components is effected by means of electrical contact areas that are preferably arranged in gridlike fashion and are electrically connected to the actual, primary contacts of the component via conductive tracks forming a rewiring plane.
The integration of such components in an electronic circuit is preferably effected by means of the known flip-chip technology. In this case, the chips are positioned with the side having the electrical contact areas downwards on the contact pads of a printed circuit board which correspond to the contact areas, and all contacts are produced simultaneously by means of a previously applied solder or conductive adhesive by component and substrate being joined to one another and soldered under the action of pressure and temperature.
The normal and shear stresses that act on the soldering connections and occur during the connecting process and, in particular, during later instances of thermal loading, for example during the artificial pre-ageing (burn-in), and are caused by the different thermal expansions of the connected materials of the component and the printed circuit board and also by possible unevennesses of the component are intended to be compensated for by preferably rubberlike, compliant elevations. The rubber-elastic properties of the elevations, which are manifested in the reversible deformability thereof, make it possible to take up and compensate for the mechanical stresses acting on the elevations. In most applications, this stress compensation has to be effected exclusively by the compliant elevations since such components, as described, do not have any further housing elements that would be suitable for compensating for or taking up the aforementioned stresses.
By way of example, such a component is described in WO 01/75969 A1, which corresponds to U.S. Patent Application Publication 2003/0067755, which applications are incorporated herein by reference. Accordingly, compliant elevations are arranged in the grid structure of the electrical contact areas and have a hill-like form and also mechanical properties comparable with those of rubber or silicone. The crest of each compliant elevation of an electronic component is covered with an electrically conductive contact area, proceeding from which a conductive track, following the slope, runs as far as the surface of the component where it realizes, together with the conductive tracks proceeding from the other compliant elevations of the component, the rewiring of the contact areas to the primary electrical contacts of the component.
However, since the conductive tracks run along the slope surface of the compliant elevations, the latter must also be able to follow compensating displacements or deformations of the compliant elevations. While that is ensured by means of conductive tracks that ascend spirally, by way of example, their transitions from the surface of the component to the compliant elevation are problematic. In particular, the pressing-together during the joining process described leads to deformations of the compliant elevation, so that, during the process, the periphery of the structure is altered in the central region and the conductive track is mechanically overloaded on account of this at the base point, which may lead to the fracture of the conductive track and to the failure of the contact.
In order to completely avoid the formation of such a critical base point, U.S. Pat. No. 5,685,885, which is incorporated herein by reference, by way of example, provides a compressible layer instead of the discrete compliant elevations, which layer covers the surface of the chip on which the contact pads thereof are arranged, and which leaves the contact pads free. The compressible layer in turn comprises further contact pads via which the integration of the chip is realized by means of solder or conductive adhesive. The electrical connection between the contact pads of the chip and those of the compressible layer is produced via flexible conductors that are routed arcuately and are encapsulated for protection each individually including the respective contact pad of the chip.
Besides the higher space requirement and the need to insert a further element for rewiring of the chip connections, such a complicated arrangement has the significant disadvantage that various additional method steps are necessary which each intrinsically may entail further reliability problems and require a high expenditure in terms of costs and time.